1. Field of the Invention
This invention relates to the field of computer systems. More particularly, this invention relates to an improved bus for communication among the various devices of a computer system.
2. Art Background
In a computer system, communication between the processor or processors and the various peripherals devices is usually accomplished by transferring information over a set of signal lines commonly referred to as a "bus". A typical bus is comprised of data lines, control lines and address lines. A common method of communication over a bus is direct memory access (DMA). During a DMA transfer, one device assumes the role of bus master while another device takes the role of slave. The bus master controls the data and control lines of the bus in order to transfer data from master to slave (write sequence) or from slave to master (read sequence). DMA has the advantage of not requiring a central processor to perform the transfer. Many devices coupled to the bus can assume the role of bus master and perform a DMA transfer.
However, a compatibility problem arises because not all devices handle data transfer in the same manner. Some devices perform "addressed data transfer" wherein the device recognizes addresses on the address lines of the bus. Other devices do not monitor the address lines of the bus, but instead require "handshake data transfer" which involves a handshake protocol. Moreover, some devices will accommodate data transfer with data 64 bits wide, while other devices may only accommodate a data width of 32 bits, or 16 bits or even 8 bits. Also, some devices require a synchronous data transfer, while others require an asynchronous data transfer.
Computer buses currently available are unable to perform both addressed data transfers and handshake data transfers. For example, a bus designed to perform addressed data transfers is not able to accommodate a peripheral device that requires handshake data transfer. To attach a peripheral device requiring handshake data transfer to such a bus requires placement of extra circuitry between the bus and the peripheral device to interface the handshake data transfer protocol of the peripheral device with the addressed data transfer protocol of the bus. Similarly, a bus designed for handshake data transfer cannot accommodate a peripheral device requiring addressed data transfer without additional circuitry to interface the peripheral device to the bus.
Buses currently available that perform data transfers between devices of varying data width have the drawback of requiring at least one extra data transfer sequence to match the proper data width. Typically, the bus master attempts to transfer data having larger width than the slave can accommodate, which causes the slave to signal an acknowledgement indicating its correct port size for data transfer. The bus master then prematurely ends the data transfer sequence and attempts another sequence later with a narrower data width. Unfortunately, the prematurely terminated data transfer followed by later retrys slows data communication over the bus.
As will be described, the present invention provides an improved computer system bus that is capable of transition between addressed data transfers and handshake data transfers "on the fly." Moreover, the computer system bus of the present invention performs burst within dynamic sizing during data transfers without prematurely terminating a data transfer sequence, and performs both synchronous and asynchronous data transfers.